Job Description

A RTL Design - Senior Staff Engineer is a highly skilled engineer responsible for designing and implementing complex digital systems using RTL (Register Transfer Level) languages like Verilog or VHDL. This role requires expertise in the development of hardware for SoCs (System-on-Chip), ASICs (Application-Specific Integrated Circuits), or FPGAs (Field-Programmable Gate Arrays), and focuses on the architecture, design, and verification of digital circuits.